Enabling Smart-Sensors via Novel Edge-AI and In-Memory Compute Paradigms: From Design, Prototype to Fabrication

Context & Background

The proliferation of IoT and Industry 4.0 will result in billions of smart sensors. Standard sensors must stream raw data to the cloud, consuming massive bandwidth and power. Edge-AI devices process data directly on the sensor, but require new hardware paradigms to run deep learning models efficiently.

Problems to be Addressed

Traditional Von Neumann architecture separation between CPU and memory causes a 'memory wall' bottleneck, limiting processing speeds and causing high power consumption on battery-operated edge sensors.

Aims and Objectives

1. Map AI/ML algorithms to low-power, hardware-friendly designs.
2. Develop FPGA prototypes of edge devices.
3. Design In-Memory Computation (IMC) circuits reaching 2000 TOPS/W.

Methodology

In collaboration with STMicroelectronics, the project uses Near-Memory and In-Memory Computation (IMC) paradigms. RTL designs are modeled using Verilog and SystemVerilog. Manpower executes synthesis, floorplanning, and clock tree design, followed on-chip silicon validation using Xilinx MPSoC boards.

Expected Outcomes

FPGA prototypes of smart sensors, silicon chip fabrication with STMicroelectronics, and highly efficient hardware accelerators for AI models.